Design of Low Power 8 bit GDI Magnitude Comparator

Low power 8 bit GDI magnitude comparator is proposed in this paper which has an advantage of minimum power dissipation, reduced propagation delay and less number of transistors required as compare to conventional CMOS magnitude comparator. Proposed GDI magnitude comparator is designed at 100MHz frequency with 1.8 v supply voltage using 180nm technology using CADENCE VLSI EDA tools. The performance analysis of proposed GDI magnitude comparator is also compared with conventional CMOS comparator, Transmission Gate Comparator and NMOS Pass Gate Comparator. Simulation of all designs have been done using SPECTRE VIRTUOSO ADE tool and the results shows that proposed GDI magnitude comparator dissipate 72.55% less power, 22.52% less propagation delay and required 65.72% less number of transistors as compare to basic CMOS magnitude comparator.